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Macros</h2></td></tr>
<tr class="memitem:a383c98c6cf46b5c9e1c40124950e03e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a383c98c6cf46b5c9e1c40124950e03e4">XCresample_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a4bcf4304e9aaf163c07d8b27755f06c0">XCresample_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="separator:a383c98c6cf46b5c9e1c40124950e03e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a644ad0f957bb97d33f18cab706e145d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a644ad0f957bb97d33f18cab706e145d5">XCresample_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#ab6f8306121516322a43ce0143ef94601">XCresample_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="separator:a644ad0f957bb97d33f18cab706e145d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">register offsets</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control register bit masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt register bit masks. It is applicable for</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Status and IRQ_ENABLE Registers </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error register bit masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Version register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Active size register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Encoding register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Coefficient bit mask and shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">General purpose macros</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">backward compatibility macros</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>To support backward compatibility following macro definition are re-defined. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt registers</div></td></tr>
<tr class="memitem:ae6f21d36c462bfb1d0bd91cfa72762aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#ae6f21d36c462bfb1d0bd91cfa72762aa">XCRE_IER_OFFSET</a>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">XCRE_IRQ_EN_OFFSET</a></td></tr>
<tr class="separator:ae6f21d36c462bfb1d0bd91cfa72762aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a705f25b13c7ec6c14dbbab653e263fe6"></a>
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          <td class="memname">#define XCRE_ACTSIZE_NUM_LINE_MASK&#160;&#160;&#160;0x1FFF0000</td>
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<p>Number of Active lines per frame (Vertical) mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>.</p>

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<a class="anchor" id="adea884db969de650a972cc4bd46ada60"></a>
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          <td class="memname">#define XCRE_ACTSIZE_NUM_LINE_SHIFT&#160;&#160;&#160;16</td>
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<p>Shift for number of lines. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>, and <a class="el" href="group__cresample__v4__0.html#gaa92fd02ee15f7f102dde33a7b2d904d3">XCresample_SetActiveSize()</a>.</p>

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<a class="anchor" id="a9f98cbfc1c9126ed40145387dc779b28"></a>
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          <td class="memname">#define XCRE_ACTSIZE_NUM_PIXEL_MASK&#160;&#160;&#160;0x00001FFF</td>
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<p>Number of Active pixels per scan line (horizontal) mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>.</p>

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<a class="anchor" id="a43ce2626e26ec592981c9fff31c4355e"></a>
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          <td class="memname">#define XCRE_COEF_DECI_MASK&#160;&#160;&#160;0x00004000</td>
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<p>Mask of Decimal part. </p>

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<a class="anchor" id="afeba8102493e8d68f3711c0de474215e"></a>
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          <td class="memname">#define XCRE_COEF_SIGN_MASK&#160;&#160;&#160;0x00008000</td>
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<p>Mask for Coefficient sign bit. </p>

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<a class="anchor" id="a8237f945f6c7bda0545995089bf6a5f6"></a>
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          <td class="memname">#define XCRE_COEFF_FRAC_MASK&#160;&#160;&#160;0x00003FFF</td>
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<p>Mask of Fractional part. </p>

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<a class="anchor" id="a6a0413d42fb2ca474c0887652e0b28d2"></a>
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          <td class="memname">#define XCRE_COEFF_MASK&#160;&#160;&#160;0x0000FFFF</td>
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<p>Coefficient mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gafe19dfb901944a21c9318301322075e6">XCresample_SetHCoefs()</a>, and <a class="el" href="group__cresample__v4__0.html#ga5f9ac7e61cd69dd5843a4a95eff0ba21">XCresample_SetVCoefs()</a>.</p>

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<a class="anchor" id="a000906b27b64ea3a083b8dcf82d8cda6"></a>
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          <td class="memname">#define XCRE_COEFF_SHIFT&#160;&#160;&#160;14</td>
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<p>Shift for decimal value. </p>

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<a class="anchor" id="a3b6c6d8486f87ee7e560f524905c18e6"></a>
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          <td class="memname">#define XCRE_COEFF_SIGN_SHIFT&#160;&#160;&#160;16</td>
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<p>Coefficient shift. </p>

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<a class="anchor" id="a3cc43348b3242c3d57ec00b1d8a49f4b"></a>
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          <td class="memname">#define XCRE_CTL_AUTORESET_MASK&#160;&#160;&#160;0x40000000</td>
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<p>Software reset - Auto-synchronize to SOF mask. </p>

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<a class="anchor" id="aaa6df80e3d96127c39d26f776a692d67"></a>
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          <td class="memname">#define XCRE_CTL_BPE_MASK&#160;&#160;&#160;0x00000010</td>
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<p>Bypass mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gac15c402d317aea7dbcdabdae1c6d8e6c">XCresample_DisableDbgBypass()</a>, <a class="el" href="group__cresample__v4__0.html#ga930ea9583c5dd76de763fae86d6b1eff">XCresample_EnableDbgByPass()</a>, and <a class="el" href="group__cresample__v4__0.html#gae8267377a15da7e199a393c47baf42e1">XCresample_IsDbgByPassEnabled()</a>.</p>

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<a class="anchor" id="a59a892889d7e272380b3187f143e2497"></a>
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          <td class="memname">#define XCRE_CTL_RESET_MASK&#160;&#160;&#160;0x80000000</td>
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<p>Software reset - instantaneous mask. </p>

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<a class="anchor" id="a236624032067fc6eab9b512945e4a1dc"></a>
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          <td class="memname">#define XCRE_CTL_RUE_MASK&#160;&#160;&#160;0x00000002</td>
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<p>Register update mask. </p>

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<a class="anchor" id="a9f8f91473ed9544ea408ab041203f53c"></a>
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          <td class="memname">#define XCRE_CTL_SW_EN_MASK&#160;&#160;&#160;0x00000001</td>
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<p>Enable mask. </p>

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<a class="anchor" id="aa66681b6d3d1c8d2d7901464355d323a"></a>
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          <td class="memname">#define XCRE_CTL_TPE_MASK&#160;&#160;&#160;0x00000020</td>
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<p>Test pattern mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#ga1f6adeb2af84970d6d20a70be30169dd">XCresample_DisableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#ga32b603c19c2afaee47a70dde41fdcaa1">XCresample_EnableDbgTestPattern()</a>, and <a class="el" href="group__cresample__v4__0.html#gae8fb855ff8ece1b628d69f9cd0eebd5a">XCresample_IsDbgTestPatternEnabled()</a>.</p>

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<a class="anchor" id="adf082abdad2a4087dd79c8e2fa86948b"></a>
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          <td class="memname">#define XCRE_ENCODING_CHROMA_MASK&#160;&#160;&#160;0x00000100</td>
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<p>Chroma parity mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#ga2871e4a4446a101e00ace372810342ce">XCresample_GetChromaParity()</a>, and <a class="el" href="group__cresample__v4__0.html#ga81bd9651d3634a4f93adc0c9aa377bd4">XCresample_SetChromaParity()</a>.</p>

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<a class="anchor" id="a55f16d3c79938d89a5f0f0fa10621800"></a>
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          <td class="memname">#define XCRE_ENCODING_CHROMA_SHIFT&#160;&#160;&#160;8</td>
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<p>Chroma parity shift. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#ga2871e4a4446a101e00ace372810342ce">XCresample_GetChromaParity()</a>.</p>

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<a class="anchor" id="a37fffbaea769fa911e7976283da2d7e1"></a>
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          <td class="memname">#define XCRE_ENCODING_FIELD_MASK&#160;&#160;&#160;0x00000080</td>
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<p>Field parity mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#ga3033cdcbecf61fea37bc9b1795636bf7">XCresample_GetFieldParity()</a>, and <a class="el" href="group__cresample__v4__0.html#gaf88e4da9bfb514e7f31550e4763b5ff1">XCresample_SetFieldParity()</a>.</p>

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<a class="anchor" id="a20167cee94dcbf66c85a5390d489ffa6"></a>
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          <td class="memname">#define XCRE_ENCODING_FIELD_SHIFT&#160;&#160;&#160;7</td>
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<p>Field parity shift. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#ga3033cdcbecf61fea37bc9b1795636bf7">XCresample_GetFieldParity()</a>.</p>

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<a class="anchor" id="a0aacdca8b7990a1d6a0e965b213bb9bc"></a>
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          <td class="memname">#define XCRE_ERR_EOL_EARLY_MASK&#160;&#160;&#160;0x00000001</td>
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<p>Error: End of Line Early mask. </p>

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<a class="anchor" id="ae1c7c77ababa0deda872bcf9585c1c13"></a>
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          <td class="memname">#define XCRE_ERR_EOL_LATE_MASK&#160;&#160;&#160;0x00000002</td>
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<p>Error: End of Line Late mask. </p>

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<a class="anchor" id="aa0df29969c8c503b72aa74ad6dbff8f5"></a>
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          <td class="memname">#define XCRE_ERR_SOF_EARLY_MASK&#160;&#160;&#160;0x00000004</td>
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<p>Error: Start of Frame Early mask. </p>

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<a class="anchor" id="aa4e7b99b55f7e72e3617c0fe3b9e3826"></a>
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<p>Error: Start of Frame Late mask. </p>

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<a class="anchor" id="ae6f21d36c462bfb1d0bd91cfa72762aa"></a>
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          <td class="memname">#define XCRE_IER_OFFSET&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">XCRE_IRQ_EN_OFFSET</a></td>
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<p>Interrupt enable</p>
<p>*..register corresponds to status bits </p>

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<a class="anchor" id="a9a38a8abeb63a5dcfbce4e1f57cf7c97"></a>
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          <td class="memname">#define XCRE_ISR_OFFSET&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga87730ba30704098d260a67036eaa6f01">XCRE_STATUS_OFFSET</a></td>
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<p>Interrupt status register. </p>

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<a class="anchor" id="a97004e97b72f36a24dc2d91e19358a99"></a>
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          <td class="memname">#define XCRE_IXR_ALLINTR_MASK&#160;&#160;&#160;0x00010003U</td>
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<p>OR of all mask. </p>

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<a class="anchor" id="a8051673328a6111720b8566bb3cf1526"></a>
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          <td class="memname">#define XCRE_IXR_EOF_MASK&#160;&#160;&#160;0x00000002</td>
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<p>End-Of-Frame mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gad3db1c393abaf5003a47b95c7399d1b7">XCresample_IntrHandler()</a>.</p>

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<a class="anchor" id="add6a498a6bc1c13fc01e91f510d342de"></a>
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          <td class="memname">#define XCRE_IXR_PROCS_STARTED_MASK&#160;&#160;&#160;0x00000001</td>
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<p>Proc started mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gad3db1c393abaf5003a47b95c7399d1b7">XCresample_IntrHandler()</a>.</p>

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          <td class="memname">#define XCRE_IXR_SE_MASK&#160;&#160;&#160;0x00010000</td>
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<p>Slave Error mask. </p>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gad3db1c393abaf5003a47b95c7399d1b7">XCresample_IntrHandler()</a>.</p>

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          <td class="memname">#define XCRE_MAX_VALUE&#160;&#160;&#160;0xFFFFFFFF</td>
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<p>32 bit maximum value </p>

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<a class="anchor" id="a00023e17dea7a5309d4f9119236654a5"></a>
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<p>Macro for sign multiplication. </p>

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<a class="anchor" id="a75692d332ef8386dd59f5ad60f72b7c7"></a>
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<p>Patch ID shift. </p>

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<a class="anchor" id="a5d8d09eb21e1e968c0450cb7dd5d516a"></a>
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          <td class="memname">#define XCRE_VER_MAJOR_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Major mask. </p>

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<a class="anchor" id="ab39e2e1a51ac5b83405a1409f3ad334a"></a>
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        <tr>
          <td class="memname">#define XCRE_VER_MAJOR_SHIFT&#160;&#160;&#160;0x00000018</td>
        </tr>
      </table>
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<p>Version Major shift. </p>

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          <td class="memname">#define XCRE_VER_MINOR_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Minor mask. </p>

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<a class="anchor" id="ae2de0988a224c4f2c0ff2c8fb99c1edd"></a>
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          <td class="memname">#define XCRE_VER_MINOR_SHIFT&#160;&#160;&#160;0x00000010</td>
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<p>Version Minor shift. </p>

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<a class="anchor" id="accd4dbc5d507c4b6f4073d012ccb3400"></a>
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          <td class="memname">#define XCRE_VER_PID_MASK&#160;&#160;&#160;0x00000F00</td>
        </tr>
      </table>
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<p>Patch ID mask. </p>

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<a class="anchor" id="a3e27a69cfbd5cf9261e123ec223e59c3"></a>
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          <td class="memname">#define XCRE_VER_REV_MASK&#160;&#160;&#160;0x0000F000</td>
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      </table>
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<p>Version Revision mask. </p>

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<a class="anchor" id="aa63888a3741a78b6a5d226ea9be119a1"></a>
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          <td class="memname">#define XCRE_VER_REV_NUM_MASK&#160;&#160;&#160;0x000000FF</td>
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<p>Revision Number mask. </p>

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<a class="anchor" id="a4ad9bb0d2ce4b4a58e639c645e7bfb28"></a>
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          <td class="memname">#define XCRE_VER_REV_SHIFT&#160;&#160;&#160;0x0000000C</td>
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<p>Version Revision shift. </p>

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<a class="anchor" id="a4bcf4304e9aaf163c07d8b27755f06c0"></a>
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          <td class="memname">#define XCresample_In32&#160;&#160;&#160;Xil_In32</td>
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      </table>
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<p>Input operations. </p>

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          <td class="memname">#define XCresample_Out32&#160;&#160;&#160;Xil_Out32</td>
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<p>Output operations. </p>

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<a class="anchor" id="a383c98c6cf46b5c9e1c40124950e03e4"></a>
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          <td class="memname">#define XCresample_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a4bcf4304e9aaf163c07d8b27755f06c0">XCresample_In32</a>((BaseAddress) + (u32)(RegOffset))</td>
        </tr>
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</div><div class="memdoc">

<p>This macro reads the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the Xilinx base address of the Chroma Resampler core </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at top of this file)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xcresample__hw_8h.html#a383c98c6cf46b5c9e1c40124950e03e4" title="This macro reads the given register. ">XCresample_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#gac15c402d317aea7dbcdabdae1c6d8e6c">XCresample_DisableDbgBypass()</a>, <a class="el" href="group__cresample__v4__0.html#ga1f6adeb2af84970d6d20a70be30169dd">XCresample_DisableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#ga930ea9583c5dd76de763fae86d6b1eff">XCresample_EnableDbgByPass()</a>, <a class="el" href="group__cresample__v4__0.html#ga32b603c19c2afaee47a70dde41fdcaa1">XCresample_EnableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>, <a class="el" href="group__cresample__v4__0.html#ga2871e4a4446a101e00ace372810342ce">XCresample_GetChromaParity()</a>, <a class="el" href="group__cresample__v4__0.html#gab4f2fab7cafe12c0dd55b63f8a4f9bb2">XCresample_GetDbgFrameCount()</a>, <a class="el" href="group__cresample__v4__0.html#ga81ee6e5159f9173134f5203f079c19d6">XCresample_GetDbgLineCount()</a>, <a class="el" href="group__cresample__v4__0.html#gadae07783fcaf65425e70d97648cbf04e">XCresample_GetDbgPixelCount()</a>, <a class="el" href="group__cresample__v4__0.html#ga3033cdcbecf61fea37bc9b1795636bf7">XCresample_GetFieldParity()</a>, <a class="el" href="group__cresample__v4__0.html#ga676b8cfd788ad69cd9c622e2a4953bed">XCresample_GetHCoefs()</a>, <a class="el" href="group__cresample__v4__0.html#ga81bd4ca76afc9607d8cc69afeb957b5f">XCresample_GetVCoefs()</a>, <a class="el" href="group__cresample__v4__0.html#ga759917fbb8599a22fdfe5619ce13a3b2">XCresample_GetVersion()</a>, <a class="el" href="group__cresample__v4__0.html#gae8267377a15da7e199a393c47baf42e1">XCresample_IsDbgByPassEnabled()</a>, <a class="el" href="group__cresample__v4__0.html#gae8fb855ff8ece1b628d69f9cd0eebd5a">XCresample_IsDbgTestPatternEnabled()</a>, <a class="el" href="group__cresample__v4__0.html#ga120e094a3de7a49d4b5e3808ad7fadd2">XCresample_SelfTest()</a>, <a class="el" href="group__cresample__v4__0.html#ga81bd9651d3634a4f93adc0c9aa377bd4">XCresample_SetChromaParity()</a>, and <a class="el" href="group__cresample__v4__0.html#gaf88e4da9bfb514e7f31550e4763b5ff1">XCresample_SetFieldParity()</a>.</p>

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<a class="anchor" id="a644ad0f957bb97d33f18cab706e145d5"></a>
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          <td class="memname">#define XCresample_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#ab6f8306121516322a43ce0143ef94601">XCresample_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes into the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the Xilinx base address of the Chroma Resampler core </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at top of this file) </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XCresample_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>

<p>Referenced by <a class="el" href="group__cresample__v4__0.html#ga1d749808d07e3987e21fb3ec7b54c3a2">XCresample_Clear_HCoef_Values()</a>, <a class="el" href="group__cresample__v4__0.html#gad3c15e9a7607730c4d6bab0bff8af610">XCresample_Clear_VCoef_Values()</a>, <a class="el" href="group__cresample__v4__0.html#gac15c402d317aea7dbcdabdae1c6d8e6c">XCresample_DisableDbgBypass()</a>, <a class="el" href="group__cresample__v4__0.html#ga1f6adeb2af84970d6d20a70be30169dd">XCresample_DisableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#ga930ea9583c5dd76de763fae86d6b1eff">XCresample_EnableDbgByPass()</a>, <a class="el" href="group__cresample__v4__0.html#ga32b603c19c2afaee47a70dde41fdcaa1">XCresample_EnableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#gaa92fd02ee15f7f102dde33a7b2d904d3">XCresample_SetActiveSize()</a>, <a class="el" href="group__cresample__v4__0.html#ga81bd9651d3634a4f93adc0c9aa377bd4">XCresample_SetChromaParity()</a>, <a class="el" href="group__cresample__v4__0.html#gaf88e4da9bfb514e7f31550e4763b5ff1">XCresample_SetFieldParity()</a>, <a class="el" href="group__cresample__v4__0.html#gafe19dfb901944a21c9318301322075e6">XCresample_SetHCoefs()</a>, and <a class="el" href="group__cresample__v4__0.html#ga5f9ac7e61cd69dd5843a4a95eff0ba21">XCresample_SetVCoefs()</a>.</p>

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